In conventional transistor-transistor logic (TTL) and diode-transistor logic (DTL), logical values corresponding to binary "1" and "0" are represented by a high level voltage V.sub.OH, for example greater than 2.5 volts and a low level voltage V.sub.OL, for example less than 0.8 volts respectively. The high level binary "1" is derived from a voltage source V.sub.cc which sources current to the output when a binary "1" is to be delivered by the logic gate. When a binary "0" is required at the output, the logic gate "sinks" the current from the output load to a low level so that the low level voltage V.sub.OL appears at the output of the logic gate. Thus the typical TTL logic gate functions by "sourcing" and "sinking" current at the output according to whether a binary "1" (high level voltage) or a binary "0" (low level voltage) is the desired outcome of previously executed logical operations. In negative logic the representation of binary "1" and "0" by high and low level voltage is reversed.
A conventional TTL bistate output is illustrated in FIG. 1. Several elements or stages can be identified in such a TTL output gate. The "pullup" 11 for sourcing current from the higher level voltage V.sub.cc corresponding to binary "1" consists of transistors Q3 and Q4 forming a Darlington transistor current source coupled between the high level voltage source V.sub.cc and the output V.sub.out. The "pulldown" element or stage 12 for sinking current and voltage from the output to ground consists of transistor Q2 with conventional squaring network transistor Q5 at its base. The phase splitter element or stage 13 consists of transistor Q1 which receives the data signal input to the gate in the form of a high or low level voltage at V.sub.in and controls the pullup and pulldown elements for either sourcing or sinking current at the output 14 as determined by the data signal input to the gate.
When a low level voltage appears at the input 15, a low voltage also appears at the base of phase splitter transistor Q1 and this transistor no longer conducts through its collector to emitter thereby turning off transistor Q2. The output V.sub.out of the gate is therefore isolated from ground. Because Q1 is nonconducting, the high level voltage V.sub.cc appears at the base of sourcing transistor Q3 permitting transistor Q3 to conduct to the base of Q4 which in turn becomes conducting and "sources" current from V.sub.cc to the output V.sub.out. The TTL logic gate is therefore inherently inverting as a binary 0 at the input V.sub.in represented by voltage level V.sub.OL generates a binary 1 at the output represented by voltage level V.sub.OH. When a binary 1 appears at the input, current from R8 supplies base drive to transistor Q1 and Q1 becomes conducting, sinking current from the base of Q3 and therefore turning off the Darlington transistor current source represented by transistors Q3 and Q4. Current from high level voltage V.sub.cc is therefore no longer sourced to the output. At the same time, pulldown transistor Q2 becomes conducting through its collector to emitter to ground as a result of the current supplied to its base and begins to discharge whatever load may be coupled to the output 14 of the gate. The speed at which transistor Q2 discharges the load drawing the output V.sub.out to the low level voltage V.sub.o depends on the base current delivered to Q2. That is, during switching while Q2 is in the linear range, the collector current of transistor Q2 equals .beta. times the base current where .beta. is the transistor current gain. During the transistion from high to low level voltage at the output 14, the pulldown element 12 must sink current not only from whatever load capacitance may be coupled at the output but also from the internal capacitance associated with the transistors and components themselves and also stray capacitance due to interconnections etc.
The speed at which the various capacitances are drained and the output voltage brought to low level, is therefore enhanced by diodes D1 and D2 indicated generally at 17. Diode D1 discharges the base of Q4 to the collector of transistor Q1 while diode D2 diverts some of the discharging load current to the collector of Q1. The increased emitter current of transistor Q1 becomes the base current to pulldown transistor Q2 thereby driving transistor Q2 harder, sinking current from the load and switching the output from binary 1 to binary 0 at a faster rate.
As shown in FIG. 1, some of the transistor and diode components are typically Schottky diodes and transistors indicated by the opposite square "hooks" in the schematic symbols. The Schottky clamping effected by an internal modification in these devices produces quicker turn-off during switching. A transistor logic output gate of the type illustrated in FIG. 1 while affording high speed switching by enhanced sinking of current during transition from high to low voltage at the output cannot provide the low impedance third state of tristate devices and is therefore unsuitable for coupling to a common bus where external voltages may be encountered.
The typical TTL tristate output gate is illustrated in FIG. 2 where components performing the same function as in the circuit FIG. 1 are similarly designated. Thus transistors Q3 and Q4 comprise the Darlington transistor current source or pullup element 11 performing the pullup function in sourcing current from V.sub.cc to V.sub.out when conducting. Transistor Q2 forms the pulldown element 12 sinking current from V.sub.out to ground when conducting. The phase splitter element 13 consisting of transistor Q1 similarly controls the pullup and pulldown elements for sourcing or sinking current at the output 14. The new element which has been added to the output gate of FIG. 2 in order to create a high impedance third state at V.sub.out is the enable gate 18 represented in part by transistor Q6. When the enable gate is conducting, base current from V.sub.cc to the Darlington transistor is diverted through the enable gate to ground. Similarly, the base current of phase splitter transistor Q1 finds a low impedance path to ground through diode D4 and the collector of enable gate transistor Q6. Ordinarily transistor Q6 is non-conducting so that the aforesaid routes to ground are blocked. In this condition, the output gate functions as a bistate output device in the manner described with reference to FIG. 1 except that feedback diodes D1 and D2 must be omitted for reasons which will hereinafter become apparent and the switching speed is slower between the high and low states. Thus, the drain of load and stray capacitances through the phase splitter collector cannot be used to drive the pulldown transistor Q2 to greater conduction to accelerate sinking of current and the transition from high to low voltage.
In order to establish a high impedance third state at V.sub.out, the enable gate 18 is activated by a signal at the base of transistor Q6 so that it becomes conducting to ground. In this state, the enable gate effectively sinks all current to the elements of the output gate including the pullup and phase splitter stages (and therefore indirectly the pulldown element) by providing a direct route to ground. With all of the elements deprived of base current, the output effectively becomes a high impedance to any exterior circuitry. In this condition, the gate will neither source nor sink current at the output and will behave effectively as if nothing were there. Such a tristate device is therefore particularly applicable and suitable for applications in which a plurality of output gates are tied together or coupled to a common bus structure. In such common bus applications only one output, that is only one of the gates coupled to the bus structure, determines the voltage (high or low) of the bus while the other outputs for the remaining gates are in the high impedance third state.
A conventional enable gate 18 of the kind incorporated in FIG. 2 and illustrated in part by the transistor Q6 is shown more fully in FIG. 2A. As presented there, the full enable gate 18 is a bistate TTL output where transistor Q6 forms the pulldown element 20 with squaring circuit 21. The other elements include the pullup element 22, splitter 23 and enable control signal input 24.
The high speed switching characteristics of the bistate output gate with feedback diodes as illustrated in FIG. 1 are, however, sacrificed by adding the enable gate to achieve the tristate TTL output illustrated in FIG. 2. To explain this compromise more fully, reference is made to FIG. 3 in which the elements and benefits of both high speed switching and tristate output as taught by the prior art and presented in FIGS. 1 and 2 are sought to be combined. Thus, FIG. 3 includes all the elements and components of both FIGS. 1 and 2 with the corresponding designations and numbering. The problem arises in attempting to combine both the enable gate 18 which makes possible the high impedance third state and the feedback diodes 17 which drain load and component capacitance through the phase splitter 13 to the base of the pulldown transistor Q2, to accelerate switching. When the enable gate 18 is activated and transistor Q6 conducting to ground, diodes D1 and D2 afford a low impedance route directly from the output 14 through the enable gate to ground. Contrary to the desired result, the third state therefore still permits a low impedance path to ground at the output.
The foregoing account represents the closest prior art and state of the art pertinent to the present invention known to the inventor. In terms of published documentation, recent representative presentations exemplifying this prior art and state of the art in DTL and TTL bistate and tristate output technology are found in MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, LOW POWER SCHOTTKY, TTL, DATA SELECTORS/MULTIPLEXERS, MONOLITHIC SILICON MIL-M-38510/309A (USAF), 4 Jan. 1978, superceding MIL-M-38510/309 (USAF), 28 Feb. 1977, Rome Air Development Center, Department of the Air Force, (RADC) (RBRD), Griffiss AFB, NY 13341. Particularly pertinent to tristate output devices in this milspec are examples of commercial type microcircuits under designation numbers 54LS251 through 54LS258 and generally 54LS microcircuits illustrated at pages 44 through 71. Additional documentation of the prior art and state of the art known to the inventor and here presented can be found in current catalogs and data books of the commercial semiconductor microcircuit and integrated circuit manufacturers such as the LOW POWER SCHOTTKY DATA BOOK of Fairchild Camera and Instrument Corporation, 464 Ellis Street, Mountain View, California 94942, Copyright 1977. Pertinent portions for tristate output devices include the chapter "Circuit Characteristics" pp. 2-3 through 2-7 and applications to buffers, bus drivers and tristate outputs in the 54LS and 74LS series of 200 and greater beginning at page 5-187.